Intel says it has cracked 5G base station market

Intel has officially launched its new SoC package aimed at RAN and vRAN base station workloads, and it said that take up from major vendors is pushing its market share target forward a year. 

Intel has said that it will be a year early to its goal to win 40% of the 5G mobile base station processor market. 

The company is launching its RAN-focussed Atom P5900 Processor – the product name for the SnowRidge SoC it announced at CES a year ago. At that time, the company said it wanted to win 40% of the mobile base station chip market by 2022. But David Fraser, Technical Sales Director, Communications Service Providers, EMEA, said, “Based on the ramp that we are seeing, driven by 5G, we will be a year early. So by 2021 we will have 40% market share in the base station category of product.”

The chip giant said in 2019 that it already had design wins with major network equipment manufacturers Ericsson, Nokia and ZTE. It looks as though pick-up within those vendors to add beef to their own custom designs has gone quicker than even Intel anticipated.

Fraser said, “We estimated last year that we would hope to be at 40% market share in this segment with this CPU by 2022, and based on the ramp that we are seeing, driven by 5G, will be a year early. By 2021 40% market share in BTS category of product.”

The 10nm System on Chip is designed as an integrated solution that includes compute, connectivity and acceleration into the same package. Fraser said that design wins were being driven by the operator need to push compute further to the edge of the network, and by enabling the virtualisation of RAN functions. It says the P5900 can get 3.4x throughput compared to software-based designs.

Fraser said, “Within the 5900 is an acceleration engine that enables the key functions that happen at that  base station node in the network to accelerate natively, and to partner with structured eASICs [where required].”

One example Fraser gave of this need for enhance processing is within RAN nodes based on architecture splits at L1/2/3 –  eg between centralised and distributed radio units. Here the acceleration can help do some of the conversion between xHaul connectivity standards and enable that partitioning at the base station, Fraser said.

Enabling fast processing for specific RAN and edge compute related use cases is one key to achieving a virtualised RAN, where software running on COTS hardware would not get the job done. Rakuten’s work with Altiostar and Intel required extensive work on accelerations to support its vision of a software RAN on a commercial hardware stack. CTO Tareq Amin prevously told TMN that running vRAN workloads straight on Intel based hardware is “not trivial”.

Amin said, “L1 requires ultra low latency to manage the radio access signalling. The challenges to do so requires you to harden the Open Stack NFVi layer. Intel had to do a lot of work on the DPDK layer, and of course enable hardware acceleration through their FPGAs.”

Ericsson and nVidia announced in late 2019 that they are exploring a GPU-based approach – using Nvidia’s GPUs for RAN workloads. At that point, Per Navinger, Head of Product Area, Networks, Ericsson, told TMN that the company is in the earlier stages of exploring the virtualisation of the lower RAN layers.

“It’s quite an interesting point in time right now, the discussion on how we can virtualise the RAN. Of course we at Ericsson deliver on purpose-built hardware and typically purpose-built is more effective and efficient. But we continuously explore and evaluate other alternatives as to how networks can be built in the future. Everyone agrees you cannot build on pure x86 server solutions – you need something that is accelerating protocol stacks, and then we see different ways of handling this acceleration. In the Nvidia discussion we are looking at how you can use GPUs with x86 and a PCI express (PCI-e) interface to build a fully virtual RAN.”

Diamond light design

Intel is also launching a structured eASIC that could be suitable for custom logic applications in RAN products, giving manufacturers a half-way house between their FPGA-based solutions and hardened ASICs. Its Diamond MESA eASIC is designed to have the same footprint as its FPGA so that vendors can migrate from the FPGA to eASIC within the product development cycle.

Intel said that Diamond MESA might suit new types of radio being designed by the host of vendors targeting Open RAN and vRAN type solutions. These can benefit from FPGA programmability and flexibility but at the cost and power structures that would come with an ASIC-based design. Currently Intel is offering designers early access to the structured ASIC programme, with product designs expected in 2022.